1. Field of the Invention
The present invention relates to the field of nonvolatile storage arrays. More particularly, the present invention relates to the field of electrically erasable and programmable ROM (EEPROM) storage arrays.
2. Description of the Prior Art
The status of the prior art in the field of electrically erasable and programmable ROM (EEPROM) storage arrays is best illustrated by considering the pertinent prior art patents and publications in this field. In that regard, one of the earlier patents in the field is U.S. Pat. No. 3,984,822. This patent describes a Double Polycrystalline Silicon Gate Memory Device. This device is programmed by the "hot electron" injection method, as distinct from the Fowler-Nordheim electron tunneling method of the present invention. The "hot electron" programming mechanism performs poorly above room temperature. This is because, as the ambient temperature increases, the "avalanche breakdown" channel current scatters charge carriers and thus decreases the efficiency of "hot" electron injection.
Another difference between the '822 patent and the present invention is that the avalanche breakdown required for the "hot electron" injection mechanism of the '822 patent requires an undesirably large amount of current, for example, a current of one milliampere. Thus, the '822 patent requires a large amount of current for successful programming. Finally, the memory device of the '822 patent is generally erasable only by exposure to ultraviolet radiation, as distinct from the electrical erasure capability of the present invention.
U.S. Pat. Nos. 4,099,196, 4,119,995, 4,314,265, and 4,701,776 all disclose the Fowler-Nordheim electron tunneling mechanism for programming and erasing employed in the present invention. However, each patent is fundamentally distinguishable from the present invention. First addressing the '196 and '265 patents, these patents are fundamentally different from the present invention because, among other things, both patents require one "Control" gate, one "Program" gate, and one "Erase" gate, whereas the present invention replaces all of these three gates with a single Control gate. Furthermore, both the '196 and '265 patents leave a net positive charge on the floating gates of the erased EEPROM transistors. As such, in both patents, the storage device is rendered conductive in the erased condition. By contrast, in accordance with the present invention, a net negative charge is always maintained on the floating gate of the EEPROM transistors. Therefore, the storage transistor of the present invention is not rendered conductive solely because that transistor is in the erased condition.
Next, turning to the '995 patent, this patent requires a select transistor in addition to the programmable storage transistor. This is because according to the '995 patent, a net positive charge is left on the floating gate of an erased storage transistor. Therefore, an additional transistor is needed to prevent the bit line connected to an unselected erased storage transistor from being pulled down to the ground voltage. By contrast, in accordance with the present invention, a net negative charge is always maintained on the floating gate. Therefore, the storage transistor of the present invention is not rendered conductive solely because that transistor is in the erased state. Thus, the present invention does not require any additional transistors to prevent a bit line connected to an unselected erased transistor from being pulled down to ground. It is noted that in a typical digital circuit, the undesirable pulling down of a bit line was a problem. However, as will be described below, the potential problem for analog storage circuits is that the column lines may be undesirably pulled high by deselected cells.
Next, discussing the '776 patent, this patent discloses a two-transistor memory cell. By contrast, the storage array of the present invention is comprised of one-transistor cells. The one-transistor cell constitutes one of the advantages of the present invention.
Further, among the relevant publications are the 1982 International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, page 108-109, and the 1989 ISSCC Digest of Technical Papers, page 132-133. The 1982 a "16K EEPROM" by National Semiconductor. The disclosure of this paper is fundamentally different from the present invention because, among other things, according to this paper each memory cell is comprised of two transistors. By contrast, the present invention utilizes one-transistor cells. As a result, the storage array of the present invention is much smaller and also much less expensive to manufacture than the storage arrays of the prior art.
Furthermore, the 1989 paper discloses a "5V-Only 256K Bit CMOS Flash EEPROM" by Texas Instruments. This paper is also fundamentally distinguishable from the present invention. For example, each cell of the EEPROM disclosed by this paper is composed of two transistors as opposed to the one-transistor cell of the present invention. Further, the EEPROM disclosed by this paper requires both negative and positive polarities of supply voltages. By contrast, the present invention operates on a single positive polarity of supply voltage.
In sum, the above prior art patents and publications have not disclosed a dense one-transistor EEPROM storage array which operates based on the electron tunneling mechanism. Moreover, the present invention is fundamentally different from the above cited prior art and other relevant prior art in many other respects which differences will be explained in the following sections of this document.
Finally, it is noted that the means for determining and generating the operating voltages to program, erase, or read an addressed EEPROM storage transistor of the present invention is disclosed in the U.S. Pat. No. 4,890,259. However, the present invention addresses entirely different aspects of the operation of an EEPROM storage array from what is disclosed by the '259 patent. In fact, as stated above, the present invention utilizes the operating voltages generated by the method disclosed in the '259 patent to implement a new EEPROM storage array. Thus, unlike the '259 patent, the present invention does not address methods of determining and generating the various operating voltages required for programming, erasing, or reading a storage EEPROM transistor. Further, the present invention is fundamentally different from the '259 patent because for example, unlike the '259 patent, the present invention addresses the operation of the individual EEPROM storage cells themselves.